The present invention relates to a frequency switching synthesizer improved in switching speed of the output frequency and in reduction of a spurious output.
One of the methods for switching the output frequency fast in a frequency switching synthesizer is the fractional dividing method. In this method, a divisor (i.e., a ratio of an original frequency and a desired output frequency) of a high frequency divider is increased cyclically, so as to realize an average divisor with an accuracy less than 1.0. As a result, a phase comparing frequency becomes higher than a desired output frequency interval, and fast switching of the output frequency is realized.
FIG. 6 shows a frequency synthesizer using the fractional dividing method in the prior art. This frequency synthesizer comprises a phase locked loop and a divisor controller circuit. The phase locked loop includes a voltage-controlled oscillator 901, a high frequency divider 902, a phase frequency comparator 904 and a low-pass filter 905. The divisor controller circuit 903 includes an accumulator 908 having a phase adder 906 and a phase register 907, a divisor adder 909, and a data register 910.
The phase adder 906 adds data given by the data register 910 and an output of the phase register 907 to make a sum that is fed back to the phase register 907. The divisor adder 909 adds one to the divisor given by the data register 910 and outputs the resulting data to the high frequency divider 902 when the accumulator 908 overflows, and otherwise passes the divisor to the high frequency divider 902.
The high frequency divider 902 divides an output signal of the voltage-controlled oscillator 901 in accordance with the divisor given by the divisor adder 909, and outputs the divided signal to the phase frequency comparator 904. The phase frequency comparator 904 compares a phase of the output signal of the high frequency divider 902 with that of a reference signal, and outputs a phase difference signal. This phase difference signal passes a low-pass filter 905 and is supplied to the voltage-controlled oscillator 901, which controls the output frequency in accordance with the phase difference signal.
As mentioned above, the divisor that the divisor controller circuit 903 gives to the high frequency divider 902 becomes one larger than the normal divisor cyclically, so an average output frequency becomes a little larger than the normal divisor. The output frequency of the voltage-controlled oscillator 901 becomes a product of the frequency of the reference signal and the average divisor of the high frequency divider 902.
However, such a frequency synthesizer using the fractional dividing method has a disadvantage. The output signal of the phase frequency comparator 904 influences and changes the controlling voltage of the voltage-controlled oscillator 901 cyclically via the low pass filter 905. This cyclic change may cause an undesired spurious signal to be superimposed on the output signal of the voltage-controlled oscillator 901. On the other hand, if a loop bandwidth is narrowed to suppress the spurious signal, it requires a long time to stabilize the controlling voltage of the voltage-controlled oscillator 901 when switching the output frequency, resulting in difficulty in performing fast switching.